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1/37 product preview october 1999 this is preliminary information on a new product now in development. details are subject to change without notice. m59dr008e m59dr008f 8 mbit (512kb x16, dual bank, page) low voltage flash memory n supply voltage Cv dd = v ddq = 1.65v to 2.2v: for program, erase and read Cv pp = 12v: optional supply voltage for fast program and erase n asynchronous page mode read C page width: 4 words C page access: 35ns C random access: 100ns n programming time C 10s by word typical C double word programming option n memory blocks C dual bank memory array: 4 mbit - 4 mbit C parameter blocks (top or bottom location) C main blocks n dual bank operations C read within one bank while program or erase within the other C no delay between read and write operations n block protection/unprotection C all blocks protected at power up C any combination of blocks can be protected Cwp for block locking n common flash interface (cfi) n 64 bit security code n erase suspend and resume modes n 100,000 program/erase cycles per block n 20 years data retention C defectivity below 1ppm/year n electronic signature C manufacturer code: 20h C device code, m59dr008e: a2h C device code, m59dr008f: a3h bga tsop48 (n) 12 x 20mm fbga48 (zb) 8 x 6 solder balls figure 1. logic diagram ai03212 19 a0-a18 w dq0-dq15 v dd m59dr008e m59dr008f e v ss 16 g rp wp v ddq v pp
m59dr008e, m59dr008f 2/37 figure 2a. fbga connections (top view) ai03213b c b a 8 7 6 5 4 3 2 1 e d f a4 a7 v pp a8 a11 a13 a0 e dq8 dq5 dq14 a16 v ss dq0 dq9 dq3 dq6 dq15 v ddq dq1 dq10 v dd dq7 v ss dq2 a2 a5 a17 w a10 a14 a1 a3 a6 du du a9 a12 a15 rp a18 dq4 dq13 g dq12 dq11 wp du figure 2b. tsop connections dq3 dq9 dq2 a6 dq0 w a3 dq6 a8 a9 dq13 a17 a10 dq14 a2 dq12 dq10 dq15 v dd dq4 dq5 a7 dq7 v pp wp ai03214 m59dr008e m59dr008f 12 1 13 24 25 36 37 48 dq8 nc nc a1 a18 a4 a5 dq1 dq11 g a12 a13 a16 a11 v ddq a15 a14 v ss e a0 rp v ss nc table 1. signal names a0-a18 address inputs dq0-dq15 data input/outputs, command inputs e chip enable g output enable w write enable rp reset/power down wp write protect v dd circuitry supply voltage v ddq input/output buffers supply voltage v pp optional supply voltage for fast program & erase v ss ground nc not connected internally du dont use as internally connected
3/37 m59dr008e, m59dr008f description the m59dr008 is an 8 mbit non-volatile flash memory that may be erased electrically at block level and programmed in-system on a word-by- word basis using a 1.65v to 2.2v v dd supply for the circuitry. for program and erase operations the necessary high voltages are generated inter- nally. the device supports asynchronous page mode from all the blocks of the memory array. the array matrix organization allows each block to be erased and reprogrammed without affecting other blocks. all blocks are protected against pro- gramming and erase at power up. blocks can be unprotected to make changes in the application and then reprotected. instructions for read/reset, auto select, write configuration register, programming, block erase, bank erase, erase suspend, erase re- sume, block protect, block unprotect, block lock- ing, cfi query, are written to the memory through a command interface using standard micropro- cessor write timings. the device is offered in tsop48 (12 x 20 mm) and in fbga48 0.75 mm ball pitch packages. when shipped all bits of the m59dr008 device are at the logical level 1. organization the m59dr008 is organized as 512kb x16 bits. a0-a18 are the address lines, dq0-dq15 are the data input/output. memory control is provided by chip enable e , output enable g and write enable w inputs. reset rp is used to reset all the memory circuitry and to set the chip in power down mode if this function is enabled by a proper setting of the con- figuration register. erase and program operations are controlled by an internal program/erase con- troller (p/e.c.). status register data output on dq7 provides a data polling signal, dq6 and dq2 provide toggle signals and dq5 provides error bit to indicate the state of the p/e.c operations. memory blocks the device features asymmetrically blocked archi- tecture. m59dr008 has an array of 23 blocks and is divided into two banks a and b, providing dual bank operations. while programming or erasing in bank a, read operations are possible into bank b or vice versa. the memory also features an erase suspend allowing to read or program in another block within the same bank. once suspended the erase can be resumed. the bank size and sector- ization are summarized in table 7. parameter blocks are located at the top of the memory ad- dress space for the m59dr008e, and at the bot- tom for the m59dr008f. the memory maps are shown in tables 3, 4, 5 and 6. the program and erase operations are managed automatically by the p/e.c. block protection against program or erase provides additional data security. all blocks are protected at power up. in- structions are provided to protect or unprotect any block in the application. a second register locks the protection status while wp is low (see block locking description). the reset command does not affect the configuration of unprotected blocks and the configuration register status. table 2. absolute maximum ratings (1) note: 1. except for the rating "operating temperature range", stresses above those listed in the table "absolute maximum ratings" may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other condition s above those indicated in the operating sections of this specification is not implied. exposure to absolute maximum rating condi - tions for extended periods may affect device reliability. refer also to the stmicroelectronics sure program and other relevant qual- ity documents. 2. depends on range. 3. minimum voltage may undershoot to C2v during transition and for less than 20ns. symbol parameter value unit t a ambient operating temperature (2) C40 to 85 c t bias temperature under bias C40 to 125 c t stg storage temperature C55 to 155 c v io (3) input or output voltage C0.5 to v ddq +0.5 v v dd , v ddq supply voltage C0.5 to 2.7 v v pp program voltage C0.5 to 13 v
m59dr008e, m59dr008f 4/37 table 3. bank a, top boot block address table 4. bank b, top boot block address size (kword) address range 4 7f000-7ffff 4 7e000-7efff 4 7d000-7dfff 4 7c000-7cfff 4 7b000-7bfff 4 7a000-7afff 4 79000-79fff 4 78000-78fff 32 70000-77fff 32 68000-6ffff 32 60000-67fff 32 58000-5ffff 32 50000-57fff 32 48000-4ffff 32 40000-47fff size (kword) address range 32 38000-3ffff 32 30000-37fff 32 28000-2ffff 32 20000-27fff 32 18000-1ffff 32 10000-17fff 32 08000-0ffff 32 00000-07fff table 5. bank b, bottom boot block address table 6. bank a, bottom boot block address size (kword) address range 32 78000-7ffff 32 70000-77fff 32 68000-6ffff 32 60000-67fff 32 58000-5ffff 32 50000-57fff 32 48000-4ffff 32 40000-47fff size (kword) address range 32 38000-3ffff 32 30000-37fff 32 28000-2ffff 32 20000-27fff 32 18000-1ffff 32 10000-17fff 32 08000-0ffff 4 07000-07fff 4 06000-06fff 4 05000-05fff 4 04000-04fff 4 03000-03fff 4 02000-02fff 4 01000-01fff 4 00000-00fff
5/37 m59dr008e, m59dr008f signal descriptions see figure 1 and table 1. address inputs (a0-a18). the address inputs for the memory array are latched during a write op- eration on the falling edge of chip enable e or write enable w , whichever occurs last. data input/output (dq0-dq15). the input is data to be programmed in the memory array or a command to be written to the command interface (c.i.) both input data and commands are latched on the rising edge of write enable w . the ouput is data from the memory array, the common flash interface, the electronic signature manufacturer or device codes, the block protection status, the configuration register status or the status regis- ter data polling bit dq7, the toggle bits dq6 and dq2, the error bit dq5. the data bus is high im- pedance when the chip is deselected, output en- able g is at v ih , or rp is at v il . chip enable (e ). the chip enable input acti- vates the memory control logic, input buffers, de- coders and sense amplifiers. e at v ih deselects the memory and reduces the power consumption to the standby level. e can also be used to control writing to the command register and to the memo- ry array, while w remains at v il . output enable (g ). the output enable gates the outputs through the data buffers during a read op- eration. when g is at v ih the outputs are high im- pedance. write enable (w ). this input controls writing to the command register and data latches. data are latched on the rising edge of w . write protect (wp ). this input gives an addition- al hardware protection level against program or erase when pulled at v il , as described in the block lock instruction description. reset/power down input (rp ). the rp input provides hardware reset of the memory (without affecting the configuration register status), and/ or power down functions, depending on the con- figuration register status. reset/power down of the memory is achieved by pulling rp to v il for at least t plph . when the reset pulse is given, if the memory is in read, erase suspend read or standby, it will output new valid data in t phq7v1 af- ter the rising edge of rp . if the memory is in erase or program modes, the operation will be aborted and the reset recovery will take a maximum ot t plq7v . the memory will recover from power down (when enabled) in t phq7v2 after the rising edge of rp . see tables 25, 26 and figure 9. v dd and v ddq supply voltage (1.65v to 2.2v). the main power supply for all operations (read, program and erase). v dd and v ddq must be at the same voltage. v pp programming voltage (11.4v to 12.6v). used to provide high voltage for fast factory program- ming. high voltage on v pp pin is required to use the double word program instruction. it is also possible to perform word program or erase instruc- tions with v pp pin grounded. v ss ground. v ss is the reference for all the volt- age measurements. device operations the following operations can be performed using the appropriate bus cycles: read array (random, and page modes), write command, output dis- able, standby, reset/power down and block locking. see table 8. read. read operations are used to output the contents of the memory array, the electronic sig- nature, the status register, the cfi, the block protection status or the configuration register status. read operation of the memory array is per- formed in asynchronous page mode, that provides fast access time. data is internally read and stored in a page buffer. the page has a size of 4 words and is addressed by a0-a1 address inputs. read operations of the electronic signature, the status register, the cfi, the block protection status, the configuration register status and the security code are performed as single asyncronous read cycles (random read). both chip enable e and output enable g must be at v il in order to read the output of the memory. write. write operations are used to give instruc- tion commands to the memory or to latch input data to be programmed. a write operation is initi- ated when chip enable e and write enable w are at v il with output enable g at v ih . addresses are latched on the falling edge of w or e whichever oc- curs last. commands and input data are latched on the rising edge of w or e whichever occurs first. noise pulses of less than 5ns typical on e , w and g signals do not start a write cycle. table 7. bank size and sectorization bank size parameter blocks main blocks bank a 4 mbit 8 blocks of 4 kword 7 blocks of 32 kword bank b 4 mbit - 8 blocks of 32 kword
m59dr008e, m59dr008f 6/37 table 8. user bus operations (1) note: 1. x = don't care. table 9. read electronic signature (as and read cfi instructions) table 10. read block protection (as and read cfi instructions) table 11. read configuration register (as and read cfi instructions) operation e g w rp wp dq15-dq0 write v il v ih v il v ih v ih data input output disable v il v ih v ih v ih v ih hi-z standby v ih xx v ih v ih hi-z reset / power down x x x v il v ih hi-z block locking v il xx v ih v il x code device e g w a0 a1 a7-a2 other addresses dq15-dq8 dq7-dq0 manufacturer code v il v il v ih v il v il 0 don't care 00h 20h device code m59dr008e v il v il v ih v ih v il 0 don't care 00h a2h m59dr008f v il v il v ih v ih v il 0 don't care 00h a3h block status e g w a0 a1 a18-a12 a7-a2 other addresses dq0 dq1 dq15-dq2 protected block v il v il v ih v il v ih block address 0 don't care 1 0 0000h unprotected block v il v il v ih v il v ih block address 0 don't care 0 0 0000h locked block v il v il v ih v il v ih block address 0 don't care x 1 0000h rp function e g w a0 a1 a7-a2 other addresses dq10 dq9-dq0 dq15-dq11 reset v il v il v ih v ih v ih 0 don't care 0 don't care reset/power down v il v il v ih v ih v ih 0 don't care 1 don't care automatic standby. when in read mode, after 150ns of bus inactivity and when cmos levels are driving the addresses, the chip automatically en- ters a pseudo-standby mode where consumption is reduced to the cmos standby value, while out- puts still drive the bus. power down. the memory is in power down when the configuration register is set for power down and rp is at v il . the power consumption is reduced to the power down level, and outputs are in high impedance, independent of the chip en- able e , output enable g or write enable w inputs. block locking. any combination of blocks can be temporarily protected against program or erase by setting the lock register and pulling wp to v il (see block lock instruction). dual bank operations. the dual bank allows to read data from one bank of memory while a pro- gram or erase operation is in progress in the other bank of the memory. read and write cycles can be initiated for simultaneous operations in different banks without any delay. status register during program or erase must be monitored using an ad- dress within the bank being modified. output disable. the data outputs are high im- pedance when the output enable g is at v ih with write enable w at v ih . standby. the memory is in standby when chip enable e is at v ih and the p/e.c. is idle. the pow- er consumption is reduced to the standby level and the outputs are high impedance, independent of the output enable g or write enable w inputs.
7/37 m59dr008e, m59dr008f instructions and commands seventeen instructions are defined (see table 14a), and the internal p/e.c. automatically han- dles all timing and verification of the program and erase operations. the status register data poll- ing, toggle, error bits can be read at any time, dur- ing programming or erase, to monitor the progress of the operation. instructions, made up of one or more commands written in cycles, can be given to the program/ erase controller through a command interface (c.i.). the c.i. latches commands written to the memory. commands are made of address and data sequences. two coded cycles unlock the command interface. they are followed by an input command or a confirmation command. the coded sequence consists of writing the data aah at the address 555h during the first cycle and the data 55h at the address 2aah during the second cycle. instructions are composed of up to six cycles. the first two cycles input a coded sequence to the command interface which is common to all in- structions (see table 14a). the third cycle inputs the instruction set-up command. subsequent cy- cles output the addressed data, electronic signa- ture, block protection, configuration register status or cfi query for read operations. in order to give additional data protection, the instructions for block erase and bank erase require further command inputs. for a program instruction, the fourth command cycle inputs the address and data to be programmed. for a double word program- ming instruction, the fourth and fifth command cy- cles input the address and data to be programmed. for a block erase and bank erase instructions, the fourth and fifth cycles input a fur- ther coded sequence before the erase confirm command on the sixth cycle. any combination of blocks of the same memory bank can be erased. erasure of a memory block may be suspended, in order to read data from another block or to pro- gram data in another block, and then resumed. when power is first applied the command interface is reset to read array. command sequencing must be followed exactly. any invalid combination of commands will reset the device to read array. the increased number of cycles has been chosen to ensure maximum data security. read/reset (rd) instruction. the read/reset instruction consists of one write cycle giving the command f0h. it can be optionally preceded by the two coded cycles. subsequent read opera- tions will read the memory array addressed and output the data read. cfi query (rcfi) instruction. common flash interface query mode is entered writing 98h at ad- dress 55h. the cfi data structure gives informa- tion on the device, such as the sectorization, the command set and some electrical specifications. tables 15, 16, 17 and 18 show the addresses used to retrieve each data. the cfi data structure contains also a security area; in this section, a 64 bit unique security number is written, starting at address 80h. this area can be accessed only in read mode by the final user and there are no ways of changing the code after it has been written by st. write a read instruction (rd) to return to read mode. table 12. commands hex code command 00h bypass reset 10h bank erase confirm 20h unlock bypass 30h block erase resume/confirm 40h double word program 60h block protect, or block unprotect, or block lock, or write configuration register 80h set-up erase 90h read electronic signature, or block protection status, or configuration register status 98h cfi query a0h program b0h erase suspend f0h read array/reset
m59dr008e, m59dr008f 8/37 auto select (as) instruction. this instruction uses two coded cycles followed by one write cy- cle giving the command 90h to address 555h for command set-up. a subsequent read will output the manufacturer or the device code (electronic signature), the block protection status or the con- figuration register status depending on the levels of a0 and a1 (see tables 9, 10 and 11). a7-a2 must be at v il , while other address input are ig- nored. the bank address is dont care for this in- struction. the electronic signature can be read from the memory allowing programming equip- ment or applications to automatically match their interface to the characteristics of m59dr008. the manufacturer code is output when the address lines a0 and a1 are at v il , the device code is out- put when a0 is at v ih with a1 at v il . the codes are output on dq0-dq7 with dq8- dq15 at 00h. the as instruction also allows the access to the block protection status. after giving the as instruction, a0 is set to v il with a1 at v ih , while a12-a18 define the address of the block to be verified. a read in these conditions will output a 01h if the block is protected and a 00h if the block is not protected. the as instruction finally allows the access to the configuration register status if both a0 and a1 are set to v ih . if dq10 is '0' only the reset function is active as rp is set to v il (default at power-up). if dq10 is '1' both the reset and the power down functions will be achieved by pulling rp to v il . the other bits of the configuration register are re- served and must be ignored. a reset command puts the device in read array mode. write configuration register (cr) instruc- tion. this instruction uses two coded cycles fol- lowed by one write cycle giving the command 60h to address 555h. a further write cycle giving the command 03h writes the contents of address bits a0-a15 to the 16 bits configuration register. bits written by inputs a0-a9 and a11-a15 are reserved for future use. address input a10 defines the sta- tus of the reset/power down functions. it must be set to v il to enable only the reset function and to v ih to enable also the power down function. at power up all the configuration register bits are reset to '0'. enter bypass mode (eby) instruction. this in- struction uses the two coded cycles followed by one write cycle giving the command 20h to ad- dress 555h for mode set-up. once in bypass mode, the device will accept the exit bypass (xby) and program or double word program in bypass mode (pgby, dpgby) commands. the bypass mode allows to reduce the overall pro- gramming time when large memory arrays need to be programmed. exit bypass mode (xby) instruction. this in- struction uses two write cycles. the first inputs to the memory the command 90h and the second in- puts the exit bypass mode confirm (00h). after the xby instruction, the device resets to read memo- ry array mode. program in bypass mode (pgby) instruc- tion. this instruction uses two write cycles. the program command a0h is written to any address on the first cycle and the second write cycle latch- es the address on the falling edge of w or e and the data to be written on the rising edge and starts the p/e.c. read operations within the same bank output the status register bits after the program- ming has started. memory programming is made only by writing '0' in place of '1'. status bits dq6 and dq7 determine if programming is on-going and dq5 allows verification of any possible error. program (pg) instruction. this instruction uses four write cycles. the program command a0h is written to address 555h on the third cycle after two coded cycles. a fourth write operation latches the address and the data to be written and starts the p/e.c. read operations within the same bank out- put the status register bits after the programming has started. memory programming is made only by writing '0' in place of '1'. status bits dq6 and dq7 determine if programming is on-going and dq5 allows verification of any possible error. pro- gramming at an address not in blocks being erased is also possible during erase suspend. double word program (dpg) instruction. this feature is offered to improve the programming throughput, writing a page of two adjacent words in parallel. high voltage (11.4v to 12.6v) on v pp pin is required. this instruction uses five write cy- cles. the double word program command 40h is written to address 555h on the third cycle after two coded cycles. a fourth write cycle latches the ad- dress and data to be written to the first location. a fifth write cycle latches the new data to be written to the second location and starts the p/e.c.. note that the two locations must have the same address except for the address bit a0. the double word program can be executed in bypass mode (dpg- by) to skip the two coded cycles at the beginning of each command.
9/37 m59dr008e, m59dr008f block protect (bp), block unprotect (bu), block lock (bl) instructions. all blocks are protected at power-up. each block of the array has two levels of protection against program or erase operation. the first level is set by the block protect instruction; a protected block cannot be pro- grammed or erased until a block unprotect in- struction is given for that block. a second level of protection is set by the block lock instruction, and requires the use of the wp pin, according to the following scheme: C when wp is at v ih , the lock status is overridden and all blocks can be protected or unprotected; C when wp is at v il , lock status is enabled; the locked blocks are protected, regardless of their previous protect state, and protection status cannot be changed. blocks that are not locked can still change their protection status, and pro- gram or erase accordingly; C the lock status is cleared for all blocks at power up; once a block has been locked state can be cleared only with a reset command. the protec- tion and lock status can be monitored for each block using the autoselect (as) instruction. pro- tected blocks will output a 1 on dq0 and locked blocks w ill output a 1 on dq1. refer to table 13 for a list of the protection states. block erase (be) instruction. this instruction uses a minimum of six write cycles. the erase set-up command 80h is written to address 555h on third cycle after the two coded cycles. the block erase confirm command 30h is similarly written on the sixth cycle after another two coded cycles and an address within the block to be erased is given and latched into the memory. table 13. protection states (1) note: 1. all blocks are protected at power-up, so the default configuration is 001 or 101 according to wp status. 2. current state and next state gives the protection status of a block. the protection status is defined by the write protect pi n and by dq1 (= 1 for a locked block) and dq0 (= 1 for a protected block) as read in the autoselect instruction with a1 = v ih and a0 = v il . 3. next state is the protection status of a block after a protect or unprotect or lock command has been issued or after wp has changed its logic value. 4. a wp transition to v ih on a locked block will restore the previous dq0 value, giving a 111 or 110. current state (2) (wp , dq1, dq0) program/erase allowed next state after event (3) protect unprotect lock wp transition 100 yes 101 100 111 000 101 no 101 100 111 001 110 yes 111 110 111 011 111 no 111 110 111 011 000 yes 001 000 011 100 001 no 001 000 011 101 011 no 011 011 011 111 or 110 (4) additional block erase confirm commands and block addresses can be written subsequently to erase other blocks in parallel, without further cod- ed cycles. all blocks must belong to the same bank of memory; if a new block belonging to the other bank is given, the operation is aborted. the erase will start after an erase timeout period of 100s. thus, additional erase confirm commands for other blocks must be given within this delay. the input of a new erase confirm command will restart the timeout period. the status of the inter- nal timer can be monitored through the level of dq3, if dq3 is '0' the block erase command has been given and the timeout is running, if dq3 is '1', the timeout has expired and the p/e.c. is erasing the block(s). if the second command given is not an erase confirm or if the coded cycles are wrong, the instruction aborts, and the device is reset to read array. it is not necessary to program the block with 00h as the p/e.c. will do this automati- cally before erasing to ffh. read operations with- in the same bank, after the sixth rising edge of w or e , output the status register bits. during the execution of the erase by the p/e.c., the memory accepts only the erase suspend es instruction; the read/reset rd instruction is ac- cepted during the 100s time-out period. data polling bit dq7 returns '0' while the erasure is in progress and '1' when it has completed. the tog- gle bit dq6 toggles during the erase operation, and stops when erase is completed. after completion the status register bit dq5 re- turns '1' if there has been an erase failure. in such a situation, the toggle bit dq2 can be used to de- termine which block is not correctly erased. in the case of erase failure, a read/reset rd instruction is necessary in order to reset the p/e.c.
m59dr008e, m59dr008f 10/37 bank erase (bke) instruction. this instruction uses six write cycles and is used to erase all the blocks belonging to the selected bank. the erase set-up command 80h is written to address 555h on the third cycle after the two coded cycles. the bank erase confirm command 10h is similarly written on the sixth cycle after another two coded cycles at an address within the selected bank. if the second command given is not an erase con- firm or if the coded cycles are wrong, the instruc- tion aborts and the device is reset to read array. it is not necessary to program the array with 00h first as the p/e.c. will automatically do this before erasing it to ffh. read operations within the same bank after the sixth rising edge of w or e output the status register bits. during the execution of the erase by the p/e.c., data polling bit dq7 re- turns '0', then '1' on completion. the toggle bit dq6 toggles during erase operation and stops when erase is completed. after completion the status register bit dq5 returns '1' if there has been an erase failure. erase suspend (es) instruction. in a dual bank memory the erase suspend instruction is used to read data within the bank where erase is in progress. it is also possible to program data in blocks not being erased. the erase suspend instruction consists of writing the command b0h without any specific address. no coded cycles are required. erase suspend is accepted only during the block erase instruction execution. the toggle bit dq6 stops toggling when the p/e.c. is suspended within 15s after the erase suspend (es) command has been writ- ten. the device will then automatically be set to read memory array mode. when erase is sus- pended, a read from blocks being erased will out- put dq2 toggling and dq6 at '1'. a read from a block not being erased returns valid data. during suspension the memory will respond only to the erase resume er and the program pg instruc- tions. a program operation can be initiated during erase suspend in one of the blocks not being erased. it will result in dq6 toggling when the data is being programmed. erase resume (er) instruction. if an erase suspend instruction was previously executed, the erase operation may be resumed by giving the command 30h, at an address within the bank be- ing erased and without any coded cycle.
11/37 m59dr008e, m59dr008f table 14a. instructions (1,2) mne. instr. cyc. 1st cyc. 2nd cyc. 3rd cyc. 4th cyc. 5th cyc. 6th cyc. rd (4) read/reset memory array 1+ addr. (3) x read memory array until a new write cycle is initiated. data f0h 3+ addr. 555h 2aah 555h read memory array until a new write cycle is initiated. data aah 55h f0h rcfi cfi query 1+ addr. 55h read cfi data until a new write cycle is initiated. data 98h as (4) auto select 3+ addr. 555h 2aah 555h read electronic signature or block protection or configuration register status until a new cycle is initiated. data aah 55h 90h cr configuration register write 4 addr. 555h 2aah 555h configura- tion data data aah 55h 60h 03h pg program 4 addr. 555h 2aah 555h program address read data polling or toggle bit until program completes. data aah 55h a0h program data dpg double word program 5 addr. 555h 2aah 555h program address 1 program address 2 note 6, 7 data aah 55h 40h program data 1 program data 2 eby enter bypass mode 3 addr. 555h 2aah 555h data aah 55h 20h xby exit bypass mode 2 addr. xx data 90h 00h pgby program in bypass mode 2 addr. x program address read data polling or toggle bit until program completes. data a0h program data dpgby double word program in bypass mode 3 addr. x program address 1 program address 2 note 6, 7 data 40h program data 1 program data 2 bp block protect 4 addr. 555h 2aah 555h block address data aah 55h 60h 01h bu block unprotect 1 addr. 555h 2aah 555h block address data aah 55h 60h d0h
m59dr008e, m59dr008f 12/37 table 14b. instructions (1,2) note: 1. commands not interpreted in this table will default to read array mode. 2. for coded cycles address inputs a11-a20 are don't care. 3. x = don't care. 4. the first cycles of the rd or as instructions are followed by read operations. any number of read cycles can occur after the com- mand cycles. 5. during erase suspend, read and data program functions are allowed in blocks not being erased. 6. program address 1 and program address 2 must be consecutive addresses differing only for address bit a0. 7. high voltage on v pp (11.4v to 12.6v) is required for the proper execution of the double word program instruction. mne. instr. cyc. 1st cyc. 2nd cyc. 3rd cyc. 4th cyc. 5th cyc. 6th cyc. bl block lock 4 addr. 555h 2aah 555h block address data aah 55h 60h 2fh be block erase 6+ addr. 555h 2aah 555h 555h 2aah block address data aah 55h 80h aah 55h 30h bke bank erase 6 addr. 555h 2aah 555h 555h 2aah bank address data aah 55h 80h aah 55h 10h es erase suspend 1 addr. (3) x read until toggle stops, then read all the data needed from any blocks not being erased then resume erase. data b0h er erase resume 1 addr. bank address read data polling or toggle bits until erase completes or erase is suspended another time data 30h
13/37 m59dr008e, m59dr008f table 15. query structure overview note: the flash memory display the cfi data structure when cfi query command is issued. in this table are listed the main sub-s ections detailled in tables 16, 17 and 18. query data are always presented on the lowest order data outputs. table 16. cfi query identification string note: query data are always presented on the lowest - order data outputs (dq7-dq0) only. dq8-dq15 are 0. offset sub-section name description 00h reserved reserved for algorithm-specific information 10h cfi query identification string command set id and algorithm data offset 1bh system interface information device timing & voltage information 27h device geometry definition flash device layout p primary algorithm-specific extended query table additional information specific to the primary algorithm (optional) a alternate algorithm-specific extended query table additional information specific to the alternate algorithm (optional) offset data description 00h 0020h manufacturer code 01h 00a3h - bottom 00a2h - top device code 02h-0fh reserved reserved 10h 0051h query unique ascii string "qry" 11h 0052h query unique ascii string "qry" 12h 0059h query unique ascii string "qry" 13h 0002h primary algorithm command set and control interface id code 16 bit id code defining a specific algorithm 14h 0000h 15h offset = p = 0040h address for primary algorithm extended query table 16h 0000h 17h 0000h alternate vendor command set and control interface id code second vendor - specified algorithm supported (note: 0000h means none exists) 18h 0000h 19h value = a = 0000h address for alternate algorithm extended query table note: 0000h means none exists 1ah 0000h
m59dr008e, m59dr008f 14/37 table 17. cfi query system interface information offset data description 1bh 0017h v dd logic supply minimum program/erase or write voltage bit 7 to 4 bcd value in volts bit 3 to 0 bcd value in 100 millivolts 1ch 0022h v dd logic supply maximum program/erase or write voltage bit 7 to 4 bcd value in volts bit 3 to 0 bcd value in 100 millivolts 1dh 0000h v pp [programming] supply minimum program/erase voltage bit 7 to 4 hex value in volts bit 3 to 0 bcd value in 100 millivolts note: this value must be 0000h if no v pp pin is present 1eh 00c0h v pp [programming] supply maximum program/erase voltage bit 7 to 4 hex value in volts bit 3 to 0 bcd value in 100 millivolts note: this value must be 0000h if no v pp pin is present 1fh 0004h typical timeout per single byte/word program (multi-byte program count = 1), 2 n s (if supported; 0000h = not supported) 20h 0000h typical timeout for maximum-size multi-byte program or page write, 2 n s (if supported; 0000h = not supported) 21h 000ah typical timeout per individual block erase, 2 n ms (if supported; 0000h = not supported) 22h 0000h typical timeout for full chip erase, 2 n ms (if supported; 0000h = not supported) 23h 0004h maximum timeout for byte/word program, 2 n times typical (offset 1fh) (0000h = not supported) 24h 0000h maximum timeout for multi-byte program or page write, 2 n times typical (offset 20h) (0000h = not supported) 25h 0004h maximum timeout per individual block erase, 2 n times typical (offset 21h) (0000h = not supported) 26h 0000h maximum timeout for chip erase, 2 n times typical (offset 22h) (0000h = not supported)
15/37 m59dr008e, m59dr008f table 18. device geometry definition offset word mode data description 27h 0014h device size = 2 n in number of bytes 28h 0001h flash device interface code description: asynchronous x16 29h 0000h 2ah 0000h maximum number of bytes in multi-byte program or page = 2 n 2bh 0000h 2ch 0002h number of erase block regions within device bit 7 to 0 = x = number of erase block regions note:1. x = 0 means no erase blocking, i.e. the device erases at once in "bulk." 2. x specifies the number of regions within the device containing one or more con- tiguous erase blocks of the same size. for example, a 128kb device (1mb) having blocking of 16kb, 8kb, four 2kb, two 16kb, and one 64kb is consid- ered to have 5 erase block regions. even though two regions both contain 16kb blocks, the fact that they are not contiguous means they are separate erase block regions. 3. by definition, symmetrically block devices have only one blocking region. m59dr008e m59dr008e erase block region information bit 31 to 16 = z, where the erase block(s) within this region are (z) times 256 bytes in size. the value z = 0 is used for 128 byte block size. e.g. for 64kb block size, z = 0100h = 256 => 256 * 256 = 64k bit 15 to 0 = y, where y+1 = number of erase blocks of identical size within the erase block region: e.g. y = d15-d0 = ffffh => y+1 = 64k blocks [maximum number] y = 0 means no blocking (# blocks = y+1 = "1 block") note: y = 0 value must be used with number of block regions of one as indicated by (x) = 0 2dh 001eh 2eh 0000h 2fh 0000h 30h 0001h 31h 0007h 32h 0000h 33h 0020h 34h 0000h m59dr008f m59dr008f 2dh 0007h 2eh 0000h 2fh 0020h 30h 0000h 31h 001eh 32h 0000h 33h 0000h 34h 0001h
m59dr008e, m59dr008f 16/37 table 19. status register bits (1) note: 1. logic level '1' is high, '0' is low. -0-1-0-0-0-1-1-1-0- represent bit value in successive read operations. 2. in case of double word program dq7 refers to the last word input. dq name logic level definition note 7 data polling '1' erase complete or erase block in erase suspend. indicates the p/e.c. status, check during program or erase, and on completion before checking bits dq5 for program or erase success. '0' erase on-going dq program complete or data of non erase block during erase suspend. dq program on-going (2) 6 toggle bit '-1-0-1-0-1-0-1-' erase or program on-going successive reads output complementary data on dq6 while programming or erase operations are on-going. dq6 remains at constant level when p/e.c. operations are completed or erase suspend is acknowledged. dq program complete '-1-1-1-1-1-1-1-' erase complete or erase suspend on currently addressed block 5 error bit '1' program or erase error this bit is set to '1' in the case of programming or erase failure. '0' program or erase on-going 4 reserved 3 erase time bit '1' erase timeout period expired p/e.c. erase operation has started. only possible command entry is erase suspend (es) '0' erase timeout period on-going an additional block to be erased in parallel can be entered to the p/e.c: 2 toggle bit '-1-0-1-0-1-0-1-' erase suspend read in the erase suspended block. erase error due to the currently addressed block (when dq5 = '1'). indicates the erase status and allows to identify the erased block. 1 program on-going or erase complete. dq erase suspend read on non erase suspend block. 1 reserved 0 reserved
17/37 m59dr008e, m59dr008f status register bits p/e.c. status is indicated during execution by data polling on dq7, detection of toggle on dq6 and dq2, or error on dq5 bits. any read attempt within the bank being modified and during program or erase command execution will automatically out- put these five status register bits. the p/e.c. au- tomatically sets bits dq2, dq5, dq6 and dq7. other bits (dq0, dq1 and dq4) are reserved for future use and should be masked (see tables 19 and 20). read attemps within the bank not being modified will output array data. data polling bit (dq7). when programming op- erations are in progress, this bit outputs the com- plement of the bit being programmed on dq7. in case of a double word program operation, the complement is done on dq7 of the last word writ- ten to the command interface, i.e. the data written in the fifth cycle. during erase operation, it outputs a '0'. after completion of the operation, dq7 will output the bit last programmed or a '1' after eras- ing. data polling is valid and only effective during p/e.c. operation, that is after the fourth w pulse for programming or after the sixth w pulse for erase. it must be performed at the address being programmed or at an address within the block be- ing erased. see figure 12 for the data polling flowchart and figure 10 for the data polling wave- forms. dq7 will also flag the erase suspend mode by switching from '0' to '1' at the start of the erase suspend. in order to monitor dq7 in the erase suspend mode an address within a block being erased must be provided. for a read operation in suspend mode, dq7 will output '1' if the read is at- tempted on a block being erased and the data val- ue on other blocks. during program operation in erase suspend mode, dq7 will have the same be- haviour as in the normal program execution out- side of the suspend mode. toggle bit (dq6). when programming or eras- ing operations are in progress, successive at- tempts to read dq6 will output complementary data. dq6 will toggle following toggling of either g , or e when g is at v il . the operation is completed when two successive reads yield the same output data. the next read will output the bit last pro- grammed or a '1' after erasing. the toggle bit dq6 is valid only during p/e.c. operations, that is after the fourth w pulse for programming or after the sixth w pulse for erase. dq6 will be set to '1' if a read operation is attempted on an erase suspend block. when erase is suspended dq6 will toggle during programming operations in a block different from the block in erase suspend. either e or g toggling will cause dq6 to toggle. see figure 13 for toggle bit flowchart and figure 11 for toggle bit waveforms. toggle bit (dq2). this toggle bit, together with dq6, can be used to determine the device status during the erase operations. during erase sus- pend a read from a block being erased will cause dq2 to toggle. a read from a block not being erased will output data. dq2 will be set to '1' during program operation and to 0 in erase operation. after erase completion and if the error bit dq5 is set to '1', dq2 will toggle if the faulty block is ad- dressed. error bit (dq5). this bit is set to '1' by the p/e.c. when there is a failure of programming or block erase, that results in invalid data in the memory block. in case of an error in block erase or pro- gram, the block in which the error occurred or to which the programmed data belongs, must be dis- carded. other blocks may still be used. the error bit resets after a read/reset (rd) instruction. in case of success of program or erase, the error bit will be set to '0'. erase timer bit (dq3). this bit is set to 0 by the p/e.c. when the last block erase command has been entered to the command interface and it is awaiting the erase start. when the erase timeout period is finished, dq3 returns to 1, in the range of 80s to 120s. table 20. polling and toggle bits mode dq7 dq6 dq2 program dq7 toggle 1 erase 0 toggle n/a erase suspend read (in erase suspend block) 1 1 toggle erase suspend read (outside erase suspend block) dq7 dq6 dq2 erase suspend program dq7 toggle 1
m59dr008e, m59dr008f 18/37 power supply power down the memory provides reset/power down control input rp . the power down function can be acti- vated only if the relevant configuration register bit is set to '1'. in this case, when the rp signal is pulled at v ss the supply current drops to typically i cc2 (see table 22), the memory is deselected and the outputs are in high impedance.if rp is pulled to v ss during a program or erase operation, this operation is aborted in t plq7v and the memory content is no longer valid (see reset/power down input description). power up the memory command interface is reset on pow- er up to read array. either e or w must be tied to v ih during power up to allow maximum security and the possibility to write a command on the first rising edge of w . supply rails normal precautions must be taken for supply volt- age decoupling; each device in a system should have the v dd rails decoupled with a 0.1f capac- itor close to the v dd , v ddq and v ss pins. the pcb trace widths should be sufficient to carry the re- quired v dd program and erase currents. table 21. program, erase times and program, erase endurance cycles (t a = 0 to 70c; v dd = v ddq = 1.65v to 2.2v, v pp = v dd unless otherwise specified) note: 1. max values refer to the maximum time allowed by the internal algorithm before error bit is set. worst case conditions pr ogram or erase should perform significantly better. 2. excludes the time needed to execute the sequence for program instruction. parameter m59dr008 unit min max (1) typ typical after 100k w/e cycles parameter block (4 kword) erase (preprogrammed) 2.5 0.15 0.4 sec main block (32 kword) erase (preprogrammed) 10 1 3 sec bank erase (preprogrammed, bank a) 2 6 sec bank erase (preprogrammed, bank b) 2 6 sec chip program (2) 58sec chip program (dpg, v pp = 12v) (2) 2.5 sec word program 200 10 10 s program/erase cycles (per block) 100,000 cycles
19/37 m59dr008e, m59dr008f table 22. dc characteristics (ta = 0 to 70c or C40 to 85c; v dd = v ddq = 1.65v to 2.2v) note: 1. sampled only, not 100% tested. 2. v pp may be connected to 12v power supply for a total of less than 100 hrs. 3. for standard program/erase operation v pp is dont care. symbol parameter test condition min typ max unit i li input leakage current 0v v in v dd 1 a i lo output leakage current 0v v out v dd 5 a i cc1 supply current (read mode) e = v il , g = v ih , f = 6mhz 10 20 ma i cc2 supply current (power down) rp = v ss 0.2v 210a i cc3 supply current (standby) e = v dd 0.2v 15 50 a i cc4 (1) supply current (program or erase) word program, block erase in progress 10 20 ma i cc5 (1) supply current (dual bank) program/erase in progress in one bank, read in the other bank 20 40 ma i pp1 v pp supply current (program or erase) v pp = 12v 0.6v 510ma i pp2 v pp supply current (standby or read) v pp v cc 0.2 5 a v pp = 12v 0.6v 100 400 a v il input low voltage C0.5 0.4 v v ih input high voltage v ddq C0.4 v ddq + 0.4 v v ol output low voltage i ol = 100a 0.1 v v oh output high voltage cmos i oh = C100a v ddq C0.1 v v pp (2,3) v pp supply voltage (program or erase) C0.4 v dd + 0.4 v double word program 11.4 12.6 v
m59dr008e, m59dr008f 20/37 table 23. capacitance (1) (t a = 25 c, f = 1 mhz) note: 1. sampled only, not 100% tested. symbol parameter test condition min max unit c in input capacitance v in = 0v 6pf c out output capacitance v out = 0v 12 pf figure 4. ac testing load circuit ai02316 v ddq / 2 out c l = 30pf c l includes jig capacitance 3.3k w 1n914 device under test table 24. ac measurement conditions input rise and fall times 4ns input pulse voltages 0 to v ddq input and output timing ref. voltages v ddq /2 figure 3. testing input/output waveforms ai02315 v ddq 0v v ddq /2
21/37 m59dr008e, m59dr008f table 25. read ac characteristics (ta = 0 to 70c or C40 to 85c; v dd = v ddq = 1.65v to 2.2v) note: 1. sampled only, not 100% tested. 2. g may be delayed by up to t elqv - t glqv after the falling edge of e without increasing t elqv . symbol alt parameter test condition m59dr008 unit 100 120 min max min max t avav t rc address valid to next address valid e = v il , g = v il 100 120 ns t av qv t acc address valid to output valid (random) e = v il , g = v il 100 120 ns t av qv 1 t pa ge address valid to output valid (page) e = v il , g = v il 35 45 ns t elqx (1) t lz chip enable low to output transition g = v il 00ns t elqv (2) t ce chip enable low to output valid g = v il 100 120 ns t glqx (1) t olz output enable low to output transition e = v il 00ns t glqv (2) t oe output enable low to output valid e = v il 25 35 ns t ehqx t oh chip enable high to output transition g = v il 00ns t ehqz (1) t hz chip enable high to output hi-z g = v il 25 35 ns t ghqx t oh output enable high to output transition e = v il 00ns t ghqz (1) t df output enable high to output hi-z e = v il 25 35 ns t axqx t oh address transition to output transition e = v il , g = v il 00ns t phq7v1 rp high to data valid (read mode) 150 150 ns t phq7v2 rp high to data valid (power down enabled) 50 50 s t plq7v rp low to reset complete during program/erase 15 s t plph t rp rp pulse width 100 100 ns
m59dr008e, m59dr008f 22/37 figure 5. random read ac waveforms ai03215 tavav tavqv taxqx telqx tehqx tglqv tglqx tghqx valid a0-a18 e g dq0-dq15 telqv valid tehqz tghqz note: write enable (w ) = high.
23/37 m59dr008e, m59dr008f figure 6. page read ac waveforms ai03216 e g dq0-dq15 a2-a18 valid a0-a1 valid valid tehqx tghqz tghqx tehqz telqv tglqv tavqv valid valid valid valid valid valid tavqv1
m59dr008e, m59dr008f 24/37 table 26. write ac characteristics, write enable controlled (t a = 0 to 70 c or C40 to 85 c; v dd = v ddq = 1.65v to 2.2v) symbol alt parameter m59dr008 unit 100 120 min max min max t avav t wc address valid to next address valid 100 120 ns t elwl t cs chip enable low to write enable low 0 0 ns t wlwh t wp write enable low to write enable high 50 50 ns t dvwh t ds input valid to write enable high 50 50 ns t whdx t dh write enable high to input transition 0 0 ns t wheh t ch write enable high to chip enable high 0 0 ns t whwl t wph write enable high to write enable low 30 30 ns t avwl t as address valid to write enable low 0 0 ns t wlax t ah write enable low to address transition 50 50 ns t ghwl output enable high to write enable low 0 0 ns t vdhel t vcs v dd high to chip enable low 50 50 s t whgl t oeh write enable high to output enable low 30 30 ns t plq7v rp low to reset complete during program/erase 15 15 s
25/37 m59dr008e, m59dr008f table 27. write ac characteristics, chip enable controlled (t a = 0 to 70 c or C40 to 85 c; v dd = v ddq = 1.65v to 2.2v) symbol alt parameter m59dr008 unit 100 120 min max min max t avav t wc address valid to next address valid 100 120 ns t wlel t ws write enable low to chip enable low 0 0 ns t eleh t cp chip enable low to chip enable high 50 50 ns t dveh t ds input valid to chip enable high 50 50 ns t ehdx t dh chip enable high to input transition 0 0 ns t ehwh t wh chip enable high to write enable high 0 0 ns t ehel t cph chip enable high to chip enable low 30 30 ns t avel t as address valid to chip enable low 0 0 ns t elax t ah chip enable low to address transition 50 50 ns t ghel output enable high chip enable low 0 0 ns t vdhwl t vcs v dd high to write enable low 50 50 s t ehgl t oeh chip enable high to output enable low 30 30 ns t plq7v rp low to reset complete during program/erase 15 15 s
m59dr008e, m59dr008f 26/37 figure 7. write ac waveforms, w controlled note: address are latched on the falling edge of w , data is latched on the rising edge of w . ai03217 e g w a0-a18 dq0-dq15 valid valid v dd tvdhel twheh twhwl telwl tavwl twhgl twlax twhdx tavav tdvwh twlwh tghwl
27/37 m59dr008e, m59dr008f figure 8. write ac waveforms, e controlled note: address are latched on the falling edge of e , data is latched on the rising edge of e . ai03218 e g w a0-a18 dq0-dq15 valid valid v dd tvdhwl tehwh tehel twlel tavel tehgl telax tehdx tavav tdveh teleh tghel
m59dr008e, m59dr008f 28/37 table 28. data polling and toggle bits ac characteristics (1) (t a = 0 to 70 c or C40 to 85 c; v dd = v ddq = 1.65v to 2.2v) note: 1. all other timings are defined in read ac characteristics table. symbol parameter m59dr008 unit min max t whq7v write enable high to dq7 valid (program, w controlled) 10 200 s write enable high to dq7 valid (block erase, w controlled) 1.0 10 sec t ehq7v chip enable high to dq7 valid (program, e controlled) 10 200 s chip enable high to dq7 valid (block erase, e controlled) 1.0 10 sec t q7vqv q7 valid to output valid (data polling) 0 ns t whqv write enable high to output valid (program) 10 200 s write enable high to output valid (block erase) 1.0 10 sec t ehqv chip enable high to output valid (program) 10 200 s chip enable high to output valid (block erase) 1.0 10 sec
29/37 m59dr008e, m59dr008f figure 9. read and write ac characteristics, rp related ai02619 dq7 w rp tplph tphq7v valid read dq7 valid tplq7v program / erase
m59dr008e, m59dr008f 30/37 figure 10. data polling dq7 ac waveforms ai03219 e g w a0-a18 dq7 ignore valid dq0-dq6/ dq8-dq15 address (within blocks) tavqv tehq7v tglqv twhq7v valid tq7vqv dq7 data polling (last) cycle memory array read cycle data polling read cycles last write cycle of program or erase instruction telqv
31/37 m59dr008e, m59dr008f figure 11. data toggle dq6, dq2 ac waveforms ai03220 e g w a0-a18 dq6,dq2 tavqv stop toggle last write cycle of program of erase instruction valid valid valid ignore data toggle read cycle memory array read cycle twhqv tehqv telqv tglqv data toggle read cycle dq0-dq1,dq3-dq5, dq7-dq15 note: all other timings are as a normal read cycle.
m59dr008e, m59dr008f 32/37 figure 12. data polling flowchart read dq5 & dq7 at valid address start read dq7 fail pass ai02574 dq7 = data yes no yes no dq5 = 1 dq7 = data yes no figure 13. data toggle flowchart read dq5 & dq6 start read dq6 fail pass ai02626 dq6 = toggles no no yes yes dq5 = 1 no yes dq6 = toggles
33/37 m59dr008e, m59dr008f table 29. ordering information scheme devices are shipped from the factory with the memory content erased (to ffffh). for a list of available options (speed, package, etc...) or for further information on any aspect of this de- vice, please contact the stmicroelectronics sales office nearest to you. table 30. revision history example: m59dr008e 100 zb 6 t device type m59 architecture d = dual bank page mode operating voltage r = 1.8v device function 008e = 8 mbit (512kb x16), dual bank: 1/half-1/half partitioning, top boot 008f = 8 mbit (512kb x16), dual bank: 1/half-1/half partitioning, bottom boot random speed 100 = 100 ns 120 = 120 ns package n = tsop48: 12 x 20mm zb = fbga48: 0.75mm pitch temperature range 1 = 0 to 70c 6 = C40 to 85c option t = tape & reel packing date revision details september 1999 first issue 10/06/99 fbga connections change (table 1, figure 2a) t whgl and t ehgl specification change (table 26, 27) 10/20/99 fbga package outline drawing and mechanical data change (table 32, figure 15) daisy chain diagrams, package and pcb connections, added (figure 16, 17)
m59dr008e, m59dr008f 34/37 table 31. tsop48 - 48 lead plastic thin small outline, 12 x 20 mm, package mechanical data symbol mm inches typ min max typ min max a 1.20 0.047 a1 0.05 0.15 0.002 0.006 a2 0.95 1.05 0.037 0.041 b 0.17 0.27 0.007 0.011 c 0.10 0.21 0.004 0.008 d 19.80 20.20 0.780 0.795 d1 18.30 18.50 0.720 0.728 e 11.90 12.10 0.469 0.476 e 0.50 C C 0.020 C C l 0.50 0.70 0.020 0.028 a 0 5 0 5 n48 48 cp 0.10 0.004 figure 14. tsop48 - 48 lead plastic thin small outline, 12 x 20 mm, package outline drawing is not to scale. tsop-a d1 e 1 n cp b e a2 a n/2 d die c l a1 a
35/37 m59dr008e, m59dr008f table 32. fbga48 - 8 x 6 balls, 0.75 mm pitch, package mechanical data symbol mm inches typ min max typ min max a 1.250 0.492 a1 0.300 0.250 0.350 0.012 0.010 0.014 a2 0.700 0.275 b 0.450 0.400 0.550 0.018 0.016 0.022 ddd 0.075 0.003 d 7.000 6.800 7.200 0.276 0.268 0.283 d1 5.250 C C 0.207 C C e 0.750 C C 0.030 C C e 7.000 6.800 7.200 0.315 0.307 0.323 e1 3.750 C C 0.148 C C sd 0.375 C C 0.015 C C se 0.375 C C 0.015 C C figure 15. fbga48 - 8 x 6 balls, 0.75 mm pitch, package outline drawing is not to scale. e1 e d1 d a2 a1 a bga-z09 ddd ball "a1" eb sd se
m59dr008e, m59dr008f 36/37 figure 16. daisy chain - package connections (top view) figure 17. daisy chain - pcb connections (top view) ai03079 c b a 8 7 6 5 4 3 2 1 e d f ai3080 c b a 8 7 6 5 4 3 2 1 e d f start stop
37/37 m59dr008e, m59dr008f information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is registered trademark of stmicroelectronics a 1999 stmicroelectronics - all rights reserved all other names are the property of their respective owners. stmicroelectronics group of companies australia - brazil - china - finland - france - germany - hong kong - india - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - u.s.a. http://www.st.com

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